Design Considerations and Fabrication Challenges of Surface Electrode Ion Trap with TSV Integration

Abstract

Surface electrode ion trap with through-silicon-via (TSV) integration enables 3D stacking of ion trap chip on an interposer to eliminate the wire-bonds on the surface electrodes and also addresses the challenge of the ever increasing complexity of surface electrode design with low-parasitic and high-density interconnect requirements. In this work, we demonstrate the design and fabrication of TSV integrated surface electrode ion trap on a 300-mm Si wafer platform. By designing the TSV arrays directly underneath the surface electrodes, the surface electrode foot print is reduced and the TSV traps show better RF performance compared to the planar traps with wire-bonding pads.