Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend

Abstract

In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling. Achieving high performance is always a key index for CPU designs. However, the resistance of interconnects has grown significantly as the dimensions of wires and vias are scaled aggressively. We present novel physical design solutions of the via pillar approach using metal layer promotion and multiple-width configurable wires. This fully automated via pillar design flow mitigates the high resistance impact and becomes indispensable in high performance designs for advanced process technologies. Maintaining power densities while aggressively shrinking chip areas is also a critical requirement, especially for mobile and IoT applications. Lowering supply voltages is one of the most effective means to reducing power consumption, especially for FinFET devices with much lower threshold voltages than planar devices. However, process and timing variation is high even for FinFET devices operating at very low voltages. We present robust ultra-low voltage IP design solutions and the current status and issues of non-Gaussian and asymmetric variation modeling for ultra-low voltage timing signoffs. Finally, advanced chip packaging is presented as a viable solution for integration and system level scaling for complex SOC systems. Specific packaging solutions can meet different requirements of system die and package size, form factor, bandwidth, power and homogeneous or heterogeneous integration. For a silicon-proven system, quantitative advantages of advanced packaging over traditional packaging in silicon thickness, thermal dissipation and voltage drop are presented. Chip packaging integration flow and requirements will also be discussed.