Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend

L. Lu
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引用次数: 17

Abstract

In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling. Achieving high performance is always a key index for CPU designs. However, the resistance of interconnects has grown significantly as the dimensions of wires and vias are scaled aggressively. We present novel physical design solutions of the via pillar approach using metal layer promotion and multiple-width configurable wires. This fully automated via pillar design flow mitigates the high resistance impact and becomes indispensable in high performance designs for advanced process technologies. Maintaining power densities while aggressively shrinking chip areas is also a critical requirement, especially for mobile and IoT applications. Lowering supply voltages is one of the most effective means to reducing power consumption, especially for FinFET devices with much lower threshold voltages than planar devices. However, process and timing variation is high even for FinFET devices operating at very low voltages. We present robust ultra-low voltage IP design solutions and the current status and issues of non-Gaussian and asymmetric variation modeling for ultra-low voltage timing signoffs. Finally, advanced chip packaging is presented as a viable solution for integration and system level scaling for complex SOC systems. Specific packaging solutions can meet different requirements of system die and package size, form factor, bandwidth, power and homogeneous or heterogeneous integration. For a silicon-proven system, quantitative advantages of advanced packaging over traditional packaging in silicon thickness, thermal dissipation and voltage drop are presented. Chip packaging integration flow and requirements will also be discussed.
满足功率、速度和面积缩放趋势的物理设计挑战和创新
在7nm及以上的先进制程技术中,半导体行业面临着几个新的挑战:(1)通过经济可行的工艺技术开发来积极扩大芯片面积;(2)通过显着增加导线和通孔电阻来充分提高先进小规模技术的性能;(3)通过不断缩小芯片面积来实现功率密度的可持续性;(4)为复杂的SOC系统提供先进的芯片封装集成解决方案。在本次演讲中,我们将探讨基于强大IP和设计方法的新型物理设计解决方案,以解决这些挑战。这些创新是通过工艺技术、IP设计和设计流程自动化的共同优化而实现的。密度标度是摩尔定律延续的最重要指标。在10nm之前,芯片面积的缩小主要是通过从根本上缩小晶体管和金属尺寸来实现的。从7nm开始,仅通过减小尺寸很难保持足够和经济的尺度。我们提出了两种具有成本效益的促成因素,FIN减少种群和EUV,以及它们相关的创新标准单元结构和物理设计流程,以实现除工艺尺寸缩放外的额外面积缩小。实现高性能一直是CPU设计的关键指标。然而,随着导线和过孔尺寸的急剧扩大,互连的电阻也显著增加。我们提出了一种新颖的通过柱方法的物理设计方案,采用金属层提升和多宽度可配置导线。这种完全自动化的通柱设计流程减轻了高阻力冲击,成为先进工艺技术高性能设计中不可或缺的一部分。保持功率密度,同时大幅缩小芯片面积也是一个关键要求,特别是对于移动和物联网应用。降低电源电压是降低功耗的最有效手段之一,特别是对于阈值电压比平面器件低得多的FinFET器件。然而,即使对于工作在极低电压下的FinFET器件,工艺和时序变化也是很大的。我们提出了鲁棒的超低电压IP设计方案,以及超低电压时序信号的非高斯和非对称变化建模的现状和问题。最后,提出了先进的芯片封装作为复杂SOC系统集成和系统级扩展的可行解决方案。特定的封装解决方案可以满足不同的系统芯片和封装尺寸、外形尺寸、带宽、功率和同质或异构集成要求。对于一个经过硅验证的系统,先进封装在硅厚度、散热和电压降方面比传统封装有量化优势。还将讨论芯片封装集成流程和要求。
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