A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet

Abstract

For the future application-friendly Internet, we have presented a router architecture that enables to interact with a variety of rich services. The proposed router snoops a traffic data stream, inspects the packet payload as well as packet headers, and stores the designated data in the associated database. The service-friendly router uses the technology of DPI (Deep Packet Inspection) for enriching services. For this purpose, high-throughput regular expression processing becomes a crucial component embedded in the router in order to extract the required information from traffic streams. Moreover, target patterns of the regular expression processing can be dynamically and frequently updated according to the applications requests. In this paper, we mainly focus on the design and evaluation of the high-throughput regular-expression processor. It accelerates the processing performance of OR matching (pipe(|)-based matching) that is familiar in various emerging applications of future Internet. The proposed regular-expression processor achieves a low overhead processing under the condition that the updates of the regular-expression patterns are frequently issued. Evaluation results show that the proposed processor achieves 6.0-Gbps throughput of regular-expression matching when using 45nm standard cell library.