An ASIC implementation of puncture and spatial stream parser for MIMO Wireless LAN system

Abstract

This paper discus an ASIC implementation of puncture and SSP for MIMO IEEE 802.11n 4×4 MIMO Wireless LAN system. We also describe its receiver counterpart block, which is SSDP and Depuncture. The biggest challenge of this work is 72 modes operation that need to be supported. The design is implemented on 90nm ASIC CMOS technology. Synthesis result for puncture and SSP reveal that the logic area is 0.025 mm2. The correspond gates count is 4.535 KGE. Circuit power consumption is 0.736 mW. The design can work at very high frequency up to 1000MHz (1GHz). Thus, it could be implemented for very high data rate applications that use MIMO OFDM techniques up to 3,750 Mbps, such as digital cinema and HDTV over wireless transmission. Meanwhile, SSDP and Depuncture synthesis shows that the logic area is 0.0309 mm2 which is equivalent with 5.581 gates. The maximum operating frequency is lower than its transmitter counterparts, only 250 MHz. Circuit power consumption is 0.209 mW.