A brief review of the various phase-frequency detector architectures

Abstract

In phase-locked loop (PLL) systems, the phase frequency detector (PFD) plays a critical role. A PFD compares the two input signals and generates outputs based on the phase difference between them. The input signals in a PFD are the reference signal and the voltage-controlled oscillator (VCO) output signal, while the output signals are the UP and DOWN signals. The VCO regulates its output frequency based on these output signals. If the UP signal is high, the VCO raises its frequency, and if the DOWN signal is high, the VCO lowers its frequency. This paper looked into and assessed a variety of PFD circuits. The effect of several topologies on the performance indicators of the PFD has been examined. Some of the performance parameters of PFDs that are compared in this study are dead zone, power dissipation, noise, and maximum operating frequency.