{"title":"A Double-Balanced I/Q Mixer with a Fully Differential Transformer-Based Quadrature Generation Network in CMOS Technology","authors":"Xiang-yang Huang, Liguo Sun, Dongwei Pang, Mingjie Liu, Jie Liu, Haiqiang Guo","doi":"10.1109/ICECE56287.2022.10048595","DOIUrl":null,"url":null,"abstract":"In this paper, a double-balanced I/Q mixer with a fully differential vertical-stacked hybrid quadrature generation network based on a high coupling on-chip transformer is demonstrated using 65 nm CMOS technology. The mixer incorporates the proposed differential vertical-stacked hybrid quadrature generation network (DVHQG) to enable good quadrature accuracy and achieve significant size reduction. The I/Q mixer exhibits a voltage gain of 6 dB while dissipating 23 mW from a 1-V supply. The magnitude imbalance and phase quadrature mismatch between I and Q channels are 0.22 dB and 0.3° from 7.7 GHz to 8.35 GHz, respectively. The achieved LO-to-RF isolation is below −72 dB. The chip dimension measures 770 × 720 μm2 where the hybrid quadrature generation network only occupies an area of 234 × 178 μm2.","PeriodicalId":358486,"journal":{"name":"2022 IEEE 5th International Conference on Electronics and Communication Engineering (ICECE)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 5th International Conference on Electronics and Communication Engineering (ICECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECE56287.2022.10048595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a double-balanced I/Q mixer with a fully differential vertical-stacked hybrid quadrature generation network based on a high coupling on-chip transformer is demonstrated using 65 nm CMOS technology. The mixer incorporates the proposed differential vertical-stacked hybrid quadrature generation network (DVHQG) to enable good quadrature accuracy and achieve significant size reduction. The I/Q mixer exhibits a voltage gain of 6 dB while dissipating 23 mW from a 1-V supply. The magnitude imbalance and phase quadrature mismatch between I and Q channels are 0.22 dB and 0.3° from 7.7 GHz to 8.35 GHz, respectively. The achieved LO-to-RF isolation is below −72 dB. The chip dimension measures 770 × 720 μm2 where the hybrid quadrature generation network only occupies an area of 234 × 178 μm2.