{"title":"Fine Grained Control Flow Checking with Dedicated FPGA Monitors","authors":"Augusto W. Hoppe, J. Becker, F. Kastensmidt","doi":"10.1109/socc49529.2020.9524751","DOIUrl":null,"url":null,"abstract":"Control flow errors are known to compose the most common type of error for embedded systems in safety-critical environments. While data protection techniques can be easily implemented with special codifications, control flow monitoring techniques either require significant hardware modifications or impose prohibitive software overheads. We propose a new control flow trace checker (CFTC) scheme which can achieve high detection rates without modifying processor hardware or adding execution overheads. Our technique can detect 97.8% of all single bit flips to control flow operations, with detection delays as fast as 0.6 µs on a Cortex-A9 CPU.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/socc49529.2020.9524751","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Control flow errors are known to compose the most common type of error for embedded systems in safety-critical environments. While data protection techniques can be easily implemented with special codifications, control flow monitoring techniques either require significant hardware modifications or impose prohibitive software overheads. We propose a new control flow trace checker (CFTC) scheme which can achieve high detection rates without modifying processor hardware or adding execution overheads. Our technique can detect 97.8% of all single bit flips to control flow operations, with detection delays as fast as 0.6 µs on a Cortex-A9 CPU.