A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system

Abstract

In the system of multi-core SoC, many specifications need to be considered to optimize interconnect bus architecture, such as the arbitration mechanism, latency, area and power consumption. This paper proposes a reconfigurable design of flexible-arbitrated crossbar to analyze the relevant factors and improve the performance and practicality with the reconfigurable implementation. Two priority matching algorithms are proposed in the design to meet more flexible-arbitrated choices for the application scenarios of multi-core SoC. Moreover, the static and dynamic reconfiguration proposed in the paper provides a valuable reference for the design of bus structure in SoC systems. Compared with the original design in the case analysis, the reconfigurable design achieves 23.3% smaller area, 15.7% less latency, and 23% power saving.