{"title":"A Design of 20MS/s 12-bit Charge Sharing SAR ADC for Ultrasound Diagnostic Medical Devices","authors":"Jung-Hyun Lee, Kangyoon Lee","doi":"10.1109/ICUFN49451.2021.9528807","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a 12-bit charge sharing analog-to-digital converter(ADC) composed of an integrated RF transceiver based on low noise, low area, and low power for ultrasound diagnostic medical devices. The proposed charge sharing DAC architecture consists of unit capacitor array and switches with low threshold voltage devices to minimize the size of the ADC. Thus, the proposed ADC had the size of 1600um x 505um with 130nm CMOS process. For the input frequency of 5MHz, the designed ADC had ENOB of 10.64-bit and SNDR of 65.82dB with the current consumption of 8.172mA for 8-channel.","PeriodicalId":318542,"journal":{"name":"2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUFN49451.2021.9528807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents the design and implementation of a 12-bit charge sharing analog-to-digital converter(ADC) composed of an integrated RF transceiver based on low noise, low area, and low power for ultrasound diagnostic medical devices. The proposed charge sharing DAC architecture consists of unit capacitor array and switches with low threshold voltage devices to minimize the size of the ADC. Thus, the proposed ADC had the size of 1600um x 505um with 130nm CMOS process. For the input frequency of 5MHz, the designed ADC had ENOB of 10.64-bit and SNDR of 65.82dB with the current consumption of 8.172mA for 8-channel.