Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study

Abstract

Trends in wireless communication systems are in the direction of multi-mode systems using different algorithms to implement the baseband processing and the channel decoding. Efficient implementation of such multi-mode support requires flexible hardware. We present design and implementation of a reconfigurable processing element for a multi-processor architecture catering to both turbo and LDPC decoding needs in the context of the WiMaX (IEEE 802.16e) standard for high-throughput applications. As a case study, we evaluate the performance of our Multi Processor System on Chip (MPSoC) architecture for a 2-D Torus/Mesh interconnect topology. Evaluation results are presented based on the communication centric parameters that include network latency, network size and can be extended to any other System on Chip (SoC) interconnect topology without loss of generality.