A 125MS/s self-latch low-power comparator in 0.35μm CMOS process

Abstract

A 125 MS/s self-latch low-power comparator in 0.35 μm CMOS process is presented. This structure is a rail-to-rail folded-cascode amplifier and a positive feedback connection of two back-to-back inverters in which only reset switches are used for controlling. A limited time is not allocated for the evaluation phase and instead the latch sequence starts itself, only after the evaluated voltage reaches to a desired level. Having sufficient time for producing the necessary evaluated voltage, of course in correct direction, guaranties the validity of the comparator operation; it means higher accuracy. Controlling the comparator is easy due to the special structure(using less controlling switches) and the layout is very compact with die size of about 34*14(μm)2. The comparator has been examined in all situations such as different corners, power supply noise of 300 m Vp-p and input voltage range of 1.6 Vp-p with 1 mV accuracy. The total power consumption of the comparator and corresponding readout circuitry is only 300 μW. The results show that the kick-back noise and the clock feed-through are reduced as well.