A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320893

T. Ueno, Tomohiko Ito, Daisuke Kurose, T. Yamaji, T. Itakura

引用次数: 5

Abstract

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, the authors employed the I/Q amplifier sharing technique (Kurose, et al., 2005) in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively

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一个1.2 V, 24mw /ch, 10位，80msample /s流水线A/D转换器

本文介绍了用于无线通信终端的10位、80 msample /s的流水线A/D转换器。为了降低功耗，作者采用了I/Q放大器共享技术(Kurose等人，2005)，其中一个放大器用于I和Q通道。此外，在所有转换阶段都使用了共源伪差分(PD)放大器，以进一步降低功率。在不使用全差分(FD)放大器的情况下，共模前馈(CMFF)技术消除了共模干扰。该转换器采用90纳米CMOS技术，在1.2 v电源下功耗仅为24 mW/ch。实测信噪比和信噪比分别为58.6 dB和52.2 dB

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Custom Integrated Circuits Conference 2006

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