Research on signal processing of inductosyn based on FPGA

Xianquan Wang, Min Wu, Jiqin Feng, Cun Dong, Lina Lou
{"title":"Research on signal processing of inductosyn based on FPGA","authors":"Xianquan Wang, Min Wu, Jiqin Feng, Cun Dong, Lina Lou","doi":"10.1109/ICICIP.2010.5565232","DOIUrl":null,"url":null,"abstract":"In order to improve reliability of Inductosyn signal processing system and save FPGA resources, the article uses a single-chip SOC system design, making the sine/cosine signal power, pulse filling phase detection and data processing integrated into an FPGA, and optimizing the signal circuit of sine / cosine through the technology of point symmetry and axial symmetry. Research on the circuit of pulsed filling phase detection, it be used to detect two singles of the phase difference and the period . Design NIOS and its interface circuits, it can detect the angle of Inductosyn, and amend the angle error with software. Experiments indicated that the designing circuit and signal processing method are correct, only need the table of 0° ~90° degrees to respectively generate the 0° ~360° sine and cosine signals, save resources of FPGA; At the same time, focus the signal generating, pulse filling phase detection, NIOS microprocessor and display interface on the FPGA, improved the reliability of system.","PeriodicalId":152024,"journal":{"name":"2010 International Conference on Intelligent Control and Information Processing","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Intelligent Control and Information Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICIP.2010.5565232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In order to improve reliability of Inductosyn signal processing system and save FPGA resources, the article uses a single-chip SOC system design, making the sine/cosine signal power, pulse filling phase detection and data processing integrated into an FPGA, and optimizing the signal circuit of sine / cosine through the technology of point symmetry and axial symmetry. Research on the circuit of pulsed filling phase detection, it be used to detect two singles of the phase difference and the period . Design NIOS and its interface circuits, it can detect the angle of Inductosyn, and amend the angle error with software. Experiments indicated that the designing circuit and signal processing method are correct, only need the table of 0° ~90° degrees to respectively generate the 0° ~360° sine and cosine signals, save resources of FPGA; At the same time, focus the signal generating, pulse filling phase detection, NIOS microprocessor and display interface on the FPGA, improved the reliability of system.
基于FPGA的感应同步器信号处理研究
为了提高感应同步信号处理系统的可靠性和节省FPGA资源,本文采用单片SOC系统设计,将正弦/余弦信号的功率、脉冲填充相位检测和数据处理集成到FPGA中,并通过点对称和轴对称技术对正弦/余弦信号电路进行优化。研究了脉冲填充相位检测电路,用于检测两单的相位差和周期。设计NIOS及其接口电路,实现感应同步器角度检测,并用软件修正角度误差。实验表明,所设计的电路和信号处理方法是正确的,只需要0°~90°的表分别生成0°~360°的正弦和余弦信号,节省了FPGA资源;同时,将信号产生、脉冲填充相位检测、NIOS微处理器和显示接口集中在FPGA上,提高了系统的可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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