Physical Design Automation for 3D Chip Stacks: Challenges and Solutions

J. Knechtel, J. Lienig
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引用次数: 14

Abstract

The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development.
3D芯片堆栈的物理设计自动化:挑战和解决方案
3D芯片堆栈的概念已经被工业界和学术界倡导多年,并被誉为最有前途的方法之一,以满足不断增长的性能,功能和功耗需求。然而,迄今为止,许多挑战阻碍了从“经典”2D芯片到堆叠3D芯片的大规模过渡。我们调查了3D芯片堆栈的主要设计挑战,特别关注它们对物理设计的影响。我们还推导了在设计自动化方面取得进展的需求,例如对统一工作流的需求。最后,我们概述了当前有希望的解决方案以及需要进一步研究和开发的领域。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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