Single processor-pool MSIMD/MIMD architectures

Abstract

In multiple SIMD/MIMD (single-instruction multiple-data/multiple-instruction multiple-data) (MSIMD/MIMD) architectures, two different types of processors are used: processing elements (PEs), to support both SIMD and MIMD partitions, and control units (CUs), to support SIMD partitions. In the existing architectures, the role of a processor to run as either PE or CU is determined only at design time. It is shown that this fixed assignment results in performance degradations. Furthermore, a single processor-pool MSIMD/MIMD architectural model with dynamic processor assignments is introduced. A cube-based single processor-pool system is presented. This system is referred to as the single-pool processor (SPP). Simulation and analysis have shown that the proposed SPP architecture offers a significantly better performance/cost than other MSIMD/MIMD systems.<>