A memory-logic separated 3D chip physical design method

Abstract

3D IC is developing rapidly, but there is no mature physical design. A 3D chip physical design method contains hierarchical process, memory and TSV localization process, as well as hierarchical physical design process is proposed in this paper. By splitting the netlist, memory and logic are layered up and down. And the upper memories and TSV cells are placed automatically by implemented the localization algorithm. Each layer can be routed separately. It is concluded that this physical design method is feasible and the processes can be compatible in 2D EDA tools.