A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme

Abstract

This work describes a 6b 1.4GS/s 65nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple row-column decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% compared to the conventional master-slave deglitching circuits. The prototype DAC with an active die area of 0.11mm2 shows an SFDR of 40.8dB and consumes 11.9mW at 1.0V and 1.4GS/s.