ChargeCache: Reducing DRAM latency by exploiting row access locality

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, V. Seshadri, Donghyuk Lee, O. Ergin, O. Mutlu
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引用次数: 138

Abstract

DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.
ChargeCache:通过利用行访问局部性来减少DRAM延迟
DRAM延迟仍然是系统性能的关键瓶颈。在这项工作中,我们开发了一种低成本的机制,称为ChargeCache,它可以更快地访问DRAM中最近访问的行,而无需修改DRAM芯片。我们的机制是基于一个关键的观察,即最近访问的行有更多的电荷,因此对同一行的后续访问可以执行得更快。为了利用这一观察结果,我们建议在内存控制器中跟踪表中最近访问的行的地址。如果稍后的DRAM请求到达该表,内存控制器将使用较低的定时参数,从而减少DRAM延迟。在指定的持续时间之后,将从表中删除行地址,以确保不会以较低的延迟访问泄漏过多费用的行。我们在各种工作负载上评估了ChargeCache,并表明它为单核和多核系统提供了显著的性能和能源优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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