A Low-power ASK Demodulator for Wireless Power and Data Transfer Systems Supporting Ultra-low Modulation Depth of 0.03%

Abstract

In wireless power and data transfer (WPDT) systems implemented with amplitude shift keying (ASK) data demodulation, the low amplitude modulation depth (MD) is usually preferred as it helps to improve energy harvesting efficiency, transmission range and stability. In this paper, a fully integrated ASK demodulator supporting ultra-low MD is proposed, which comprises a two-stage self-biased shifted limiter (SSL) that provides sufficient conversion gain and operates at low power consumption by introducing an adaptive biasing circuit. This structure is implemented in 0.18 $\mu \mathbf{m}$ high-voltage Bipolar-CMOS-DMOS technology. The detectable MD is measured as low as 0.03%, while the power consumption is only 52.5 $\mu \mathbf{W}$.