Highly configurable programmable built-in self test architecture for high-speed memories

Abstract

With the rapid growth in the number, the size, and the density of embedded memories in the current generation of microprocessors, developing high coverage memory built-in self-test (MBIST) engines has become increasingly challenging. The MBIST engine should provide high defect coverage and accurate diagnostic capabilities. Furthermore, MBIST engine should be accessible not only at the tester but also at the system. We present our work to develop a MBIST architecture that fulfils all such requirements and supports various flavors of embedded SRAMs. Extensive utilization of the proposed architecture in our products will result in increased productivity by reducing the development time and the verification and productization effort.