Reduced access time with WTA sense amplifier for standard CMOS SRAM cell

Abstract

In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better performance of our proposed design compared to the conventional cross-coupled amplifier. The design and simulation is carried out in Cadence virtuoso platform with UMC 0.18μm process technology.