A slew-rate controlled output driver with one-cycle tuning time

Abstract

A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1 V/ns to 3.6 V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18 um CMOS process, and the control block consumes 13.7 mW at 1 Gbps.