A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors

Abstract

Application-specific instruction set processor (ASIP) has emerged as an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy-efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration (e.g., automatic custom instruction identification and synthesis), the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach to utilize the custom registers for reducing the data traffic between the processor and memory through efficient communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that promising performance improvements can be achieved.