Fast recoverable heterogeneous quad-core lockstep architecture

Abstract

With the increasing demand of industry and automobile for reliability, various redundant software and hardware technologies are introduced into system design. In this paper, we present a fast recoverable heterogeneous quad-core lockstep architecture to mitigate single event upset (SEU) and common-mode failure(CMF) problems. Two ARM processors and Two RISC-V processors are integrated in a loosely-coupled lockstep mode and a recovery scheme is implemented without frequent processor context saving.