StarCore: a high-speed ATM switching system

Abstract

This paper presents a cell scheduling algorithm and its hardware implementation used in an ATM switching system, StarCore. Output contention is resolved by the hardware arbiters in a weighted round-robin fashion, which takes account of the bandwidths allocated to the virtual circuits as well as the priority classes. The arbiter consists of primitive logic gates, which are beneficial for CMOS VLSI implementation, and therefore it gives high-speed arbitration. The circuit simulations indicate that the time for the arbitration of a 64-input switch is 4.2 nsec using 0.7-/spl mu/m CMOS VLSI technology. The simulations show that StarCore provides lower cell loss probabilities than the conventional round-robin method.