Parallel multipliers based on horizontal compressors

Abstract

Two new implementations of parallel multipliers, based on iterative arrays of logic cells are presented in this paper. Both are able to compute the product of two n bit numbers with a delay of n cells, rather 2n−l as in classical structures. The high speed operation is obtained by using pure horizontal compressors, to accelerate the horizontal signal propagation, and by adopting a suitable array structure, to shorten the vertical signal propagation. The cost and performance advantages over similar structures based on vertical compressors are discussed.