A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler

Abstract

This paper presents a CMOS analog multiplexer for a DAC bandwidth tripler. The bandwidth tripler extends the bandwidth of the DACs three times without generating image signals. We revealed the effect of the non-linearity of the AMUX in the bandwidth tripler, and pseudo differential switches were used to reduce the distortions. To compensate for the limited performance of CMOS devices, a broadband matching circuit was inserted into the output of the AMUX. Post-layout simulation results demonstrated a 50 Gbps PAM4 signal generation with a small power consumption of 49 mW. The power efficiency of the AMUX is only 0.98 pJ/bit, which is superior to the previous work.