Environmental Challenges for 45-nm and 32-nm node CMOS Logic

Abstract

The objective of this work is to understand the materials and energy requirements, and emissions associated with new semiconductor manufacturing technology nodes. Current and near-future CMOS technologies (for the 45-nm and 32-nm nodes) are investigated using an inventory based on bottom-up process data. The process flow of the CMOS chip is modeled by updating an existing inventory analysis (for 130 nm node devices) to include strained Si channels, metal gates, 10 layers of interconnect and high-k gate dielectrics used in 45-nm and 32-nm CMOS nodes. Conclusions are made concerning emissions of new materials and trends in life cycle energy consumption of logic devices.