Optimization of a reliable Network on Chip dedicated to partial reconfiguration

Abstract

We present an optimization of reliable Network on Chip (NoC) structure dedicated to dynamic reconfigurable systems (DRS) based on FPGA. The originality of our approach is based on a strategic placement of router incorporating elements of dependability. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network and reduce the cost of area, the latency of the data packets and the power consumption. The proposed approach can be applied to the majority NoC topologies.