A Compact 3.9-4.7 GHz, 0.82 mW All-Digital PLL with 543 fs RMS Jitter in 28 nm CMOS

Abstract

This paper presents an ultra-low power all-digital phase-locked loop (ADPLL) with 543 fs rms jitter. Fabricated in a commercial 28-nm CMOS technology, the ADPLL covers 3.95-to-4.685 GHz (17% fractional tuning range). Measured phase noise (PN) at 100 kHz, 1 MHz and 10 MHz offsets is -98.3, -104.1 and -126.5 dBc/Hz respectively (referenced to 4.6 GHz). Integrated PN of less than -36 dBc Single Side Band (SSB) was recorded for 10 kHz to 20 MHz integration range. The ADPLL consumes $572 {\mu} A$ from a 0.8V analog supply and $400 {\mu} A$ from a 0.9 V digital supply, for a total power consumption of 0.82 mW. The ADPLL occupies an active area of less than 0.105 mm2.