HDL implementation of 128- bit Fused Multiply Add unit for multi mode SoC

Abstract

Binary 128 arithmetic finds a hard in floating point application of Quadruple Precision. The major component of 128 bit Fused Multiply Add (FMA) unit with multimode operations are Alignment Shifter, Normalization shifter, Dual Adder by CLA. The main contribution of this paper is to reduce the latency. The technical challenges in existing FMA architectures are latency and higher precision. The precision gets affected by the repeated occurrence of fractional part. In order to reduce the latency the dual adder is designed by using compound Adder and the latency of overall architecture gets reduced up to 30-40%. In this paper the total delay of dual adder designed using compound adder is found to be 5.776 ns. Simultaneously to get higher precision we design namely Alignment Shifter and Normalization Shifter in the FMA unit by using Barrel Shifter as this Alignment Shifter and Normalization Shifter will have less precision, but since replacement of these blocks by Barrel Shifter will result into higher precision.