An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing

Abstract

The emergence of nanophotonic devices has enabled to design integrated optical circuits for ultra-high speed on-chip signal processing. This paper proposes an optical implementation of an approximate parallel multiplier for two n-bit integers. The key to ultra-high speed processing is to reduce the number of OptoElectric (OE) converters on a critical path since the OE converters dominantly determine the operating speed of the multiplier. For any n, the proposed approximate multiplier has only three OE converters on a critical path with a deterministic error (11% at the worst case). On the other hand, the number of the counterparts of the conventional parallel multiplier increases as $n$ increases, which implies that the proposed multiplier with large $n$ exhibits much better operating speed than the conventional optical parallel multiplier. Numerical evaluation for n = 16 shows that the proposed multiplier exhibits a 106 ps latency which is 49% less than that of the conventional optical multiplier.