Hybrid Deep Learning Pipeline for Advanced Electrical Wafer Defect Maps Assessment

Abstract

Detection and identification of production defects in semiconductor industry is a key process to allow effective quality control of manufacturing. The advent of new technologies including Silicon and Silicon Carbide, highlights the necessity to have a robust detection system of wafer defects.The Electrical Wafer Sorting (EWS) stage based on defects map electrical analysis is suitable to spot anomalies and defect patterns in the wafer. This time consuming phase enables semiconductor companies to optimize and improve manufacturing process also through the usage of modern deep learning approaches. The proposed pipeline addresses the need to have a full-automatic wafer manufacturing defects identification system based on the EWS wafer map intelligent analysis and by using an approach based on a Deep Convolutional Neural Network combined with an unsupervised sub-system. The collected experimental results confirmed the robustness of the proposed approach.