Design and Implementation of Image Chaotic Communication via FPGA Embedded Ethernet Transmission

Abstract

In this paper, a novel approach for digital image chaotic communication via FPGA embedded Ethernet transmission is proposed. Based on Euler algorithm and variable ratio expansion transformation, by C language programming under the Linux operating system, the continuous time 8-scroll Chua system is converted to the discrete sequence used to encrypt and decrypt image on the FPGA-based platform. According to the principle of driving-response synchronization, a scheme for chaotic communication of a 512×512BMP static color image is implemented via embedded Ethernet transmission on the FPGA-based platform with XUP Virtex-II Pro chip. Moreover, the system design, software simulation and hardware implementation results are also given.