Yongxin Li, Nilanjan Pal, Tianyu Wang, M. Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, P. Hanumolu
{"title":"A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy","authors":"Yongxin Li, Nilanjan Pal, Tianyu Wang, M. Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, P. Hanumolu","doi":"10.1109/CICC53496.2022.9772819","DOIUrl":null,"url":null,"abstract":"The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"11979 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC53496.2022.9772819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.