A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Abstract

Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.