Design and implementation of a parity-based BIST scheme for FPGA global interconnects

Abstract

This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme.