Performance Characteristics of Parallel and Pipelined Implementation of FIR Filters in FPGA Platform

Abstract

In this paper, we present area-delay and power-delay characteristics against varying levels of parallel and pipelined implementations of finite impulse response (FIR) filter in FPGA platform for high throughput applications. From the synthesis results, it has been observed that the parallel systolic architecture (PSA) has a better overall resource utilization based on the area-delay product and power-delay product. The area-delay product of the PSA is 40% lesser than the parallel retimed broadcast architecture (PRBA) and almost one-third that of the unfolded direct and broadcast form parallel architectures for filter order, N = 8 and L = 8. Moreover, it exhibits better area-delay products for higher N. The power-delay products of PSA are marginally higher than PRBA, but one-fourth of the unfolded direct and broadcast form parallel architectures. The four parallel architectures have been implemented on Virtex-II 1000 device (XC2V1000BG575-4) and Virtex-II 8000 device (XC2V8000FF1152-4) for filter orders 8 and 32 respectively.