Interconnect BIST based new self-repairing of TSV defect in 3D-IC

Abstract

This paper presents an Interconnect Built-In Self-Repair (IBISR) strategies for Through Silicon Via (TSV) in three dimension integrated circuits (3D-IC). The proposed IBISR structure focuses on testing of specific defective TSV by using Interconnect BIST methodology. After interconnect test, the result giving will be delivered to the BISR structure for repairing TSV defects. Additionally, a parallel processing approach is presented of the proposed IBISR structure to up grit speed of operations of test and repair. Experimental results demonstrate that the proposed IBISR scheme can achieve the good performance in repair rate and yield with little area overhead penalty.