Thermal capacitance matching in 3D many-core architectures

Abstract

While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face with the significant challenge of small, localized hotspots with very large power dissipation due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this paper, a new thermal management solution is proposed that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. We show that this results in an up-to-twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required.