A High-Speed Pipelined-SAR ADC with Resistor-based Self-biasing RAMP

Abstract

This paper proposes a two-stage Pipelined-SAR ADC for high-speed, high-resolution and low-power applications. The sub-ADCs adopt the lower plate sampling and upper plate sampling asynchronous SAR logic respectively. The inter-stage amplifier adopts ring amplifier. The self-biasing RAMP is based on a variable resistor, which decreases the settling time of ring amplifier while maintaining low power consumption and sufficient phase margin. In addition, the first stage sub-ADC uses two parallel routes to sample and transfer residue voltage alternately, which further enhance the sample rate. A prototype ADC is designed and simulated in TSMC40nm CMOS technology with a standard 1.1 V supply voltage. The SNDR and ENOB is 55.34 dB and 8.9bit respectively from the simulation results, with a Nyquist frequency input sampled at 200 MS/s, and figure of merit of 35.4fJ/conversion-step.