Thrifty Technology Mapping With Rich Libraries

Abstract

Technology mapping is used during logic synthesis to bind a circuit description to a given library of cells. The mapping process is divided into the phases of decomposition, matching and covering. We have developed a method of matching which is functional in nature, as opposed to the usual structural approach. The new matching technique allows the use of very large libraries. New techniques for decomposition and covering are also described. For circuits with fanout, we propose several heuristics for determining when to share and when to duplicate logic. These heuristics are quantitatively compared using a set of benchmark circuits.