Modified booth multiprecision multiplier with scalable voltage and frequency units

Abstract

Multipliers are considered to be an important component in DSP applications like filters. Designing high-speed multipliers with low power have substantial research interest. Modified Booth Multiprecision Multiplier (MBMP) reduces the power consumption by selecting the small precision multipliers in accordance with the selection of input operands selector. The large area overhead can be reduced by reusing 9 bit and 17 bit multipliers to perform a higher precision multiplication such as 16 × 16, 32 × 32 respectively. The design of multiplier is done using modified booth algorithm which reduces total number partial products from N to N/2 so that the computational complexity is reduced. The dynamic frequency scaling and voltage scaling units provide the required frequency and supply voltage based on the run time workload. Finally we can yield the improved power performance while comparing the proposed MBMP multiplier with the conventional fixed width multiplier.