Rounded edge mesa for submicron SOI CMOS process

Abstract

Different isolation features have been proposed for silicon on insulator (SOI): LOCOS, mesa, and reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. The rounded edge mesa (REM) presented allows accurate control of the gate dimensions without shorts. A 0.8 mu m DLM CMOS process was run on ZMR (zone-melting recrystallization) SOI films thinned down to 150 nm. After the REM formation, the pad oxide is stripped and a 15 nm gate oxide is grown followed by a 380 nm N+-polysilicon film deposition. A classical gate etch is then applied. The absence of residues as studied by measuring the resistance of 22 mm long 0.8 mu m spaced 0.8 mu m wide interdigitated polysilicon fingers running on mesas. The absence of subthreshold leakage or bumps in the subthreshold slope confirms that this technique prevents the formation of sidewall parasitic channels.<>