Scheduling of stream programs onto SPM enhanced processors with code overlay

Abstract

Scratch Pad Memories (SPM) have emerged as an alternative to caches in embedded processor architectures due to their lower power consumption, smaller chip area and superior performance. However, the advantages of SPM come at the expense of increased load on the programmer as she is responsible for memory management. Consequently, there is a need for novel compilation for mapping applications onto SPM enhanced embedded processors. Stream programs (that describe a large class of embedded applications) demonstrate stable memory access patterns, and are particularly suitable for SPM based processors. In this paper we present a heuristic approach for scheduling and compiling streaming applications (modeled by synchronous data flow graphs) for SPM enhanced processors. The technique maximizes the application performance by minimizing code overlay overheads that are introduced when executing a large code base on a smaller sized SPM. We also present an extension of our approach that further reduces the overheads by selective code pre-fetching. The effectiveness of our approaches is evaluated by compiling ten streaming application onto one Synergistic Processing Engine (SPE) of the IBM Cell processor.