HyperPipelining of High-Speed Interface Logic

Abstract

The throughput needs of networking designs on FPGAs are constantly growing -- from 40Gbps to 100Gbps, 400Gbps and beyond. A 400G Ethernet MAC needs to process wide data at high speeds to meet the throughput needs. Altera recently introduced HyperFlexTM [1][2][3], a change to the fabric architecture aimed to facilitate massive pipelining of FPGA designs -- allowing them to run faster and hence alleviate the congestion that is caused by widening datapaths beyond 512b or 1024b. Though it seems counterintuitive it can be easier to close timing at 781 MHz for a 640b datapath than at 390 MHz for a 1280b datapath when wire congestion is taken into account. This presentation will discuss some of the practical details in implementing high-throughput protocols such as Ethernet and Interlaken, how we address these traditionally and how the design of the cores is modified with HyperPipelining. We will discuss alternative development styles for control and datapath logic, strategies for wire planning to avoid congestion, the throughput limits of FPGA routing networks, common timing closure issues and how to alleviate them, and how to pipeline intelligently. This presentation is thus partly a tutorial in the issues of making a 400G FPGA design close timing, and partly a case study of using HyperFlex on an FPGA design.