H.264/AVC interpolation optimization

Abstract

This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.