A digitally controlled CMOS RF power amplifier

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986316

M. Hella, M. Ismail

引用次数: 1

Abstract

This paper presents the design, and implementation of an RF power amplifier in a standard 0.35 /spl mu/m CMOS technology. The amplifier is capable of delivering 16.5 dBm of output power at 1.85 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 30%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. Measurement results of the fabricated chip are included.

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一种数字控制CMOS射频功率放大器

本文介绍了一种标准0.35 /spl mu/m CMOS工艺下射频功率放大器的设计与实现。该放大器能够在1.85 GHz下使用3.3 V电源提供16.5 dBm的输出功率，总体测量功率增加效率(PAE)为30%。功率放大器采用AB类输出级，这代表了效率和线性之间的折衷。最后给出了所制芯片的测量结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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