On Implementation of LUT with Large Numbers of Inputs (Abstract Only)

Abstract

A LUT is implemented with a set of flipflops which are connected to a series of multiplexers, or alternatively with a small memory, and needs exponentially many storage elements with respect to the numbers of inputs. Due to this FPGA uses LUTs having around 6 inputs, but LUTs with larger numbers of inputs may be better from various performance viewpoints as well as its applications to flexible logic debugging and Engineering Change Order (ECO) as there are less interconnects among LUTs. Such LUTs may accommodate changes of designs including logic debugging and ECO. We discuss implementations for LUTs having relatively large numbers of inputs, such as 12-inputs. If we implement a single LUT with 12-inputs, we need 212 = 4,096 storage elements. On the other hand, we can construct 12-input subcircuits of fixed topologies only with sets of LUTs having small numbers of inputs, such as 4-inputs. Although such subcircuits can only realize very small subsets of all possible logic functions with 12-inputs, if they can realize most of the logic functions we need for actual designs by only reprogramming the sets of 4-input LUTs, they are practically worthwhile to be used. We present several such fixed-topology subcircuits as well as automatic compilation methods from given logic functions. Experimental results show almost all functions (more than 99%) which appear benchmark circuits with partially disjoint decomposability can be implemented by the proposed topologies. Sophisticated circuit portioning methods can always generate networks of subcircuits with partially disjoint decomposability.