Andrea Pizzarulli, G. Montagna, M. Pini, S. Salerno, N. Lofù, Gianluca Sensalari
{"title":"Reconfigurable and simultaneous dual band Galileo/GPS front-end receiver in 0.13μm RFCMOS","authors":"Andrea Pizzarulli, G. Montagna, M. Pini, S. Salerno, N. Lofù, Gianluca Sensalari","doi":"10.1109/PLANS.2008.4569990","DOIUrl":null,"url":null,"abstract":"A reconfigurable and simultaneous dual band Galileo/GPS front-end receiver has been realized on 0.13-mum RFCMOS technology. The front-end uses only one fixed frequency PLL and VCO on a superheterodyne architecture to down-convert two RF (radio frequency) signals into two IF (intermediate frequency) signals in the range of 50 MHz to 150 Mhz. L1 and E1 signals are directly converted on one channel with one mixing stage. L2, E6, E5, E5a, E5b signals are down-converted with a double stage (two mixers) conversion. The two IF down-converted channels are filtered and then undersampled by two on chip ADC (analog to digital converter). The satellite channels can be selected and reconfigured only by changing the ADC sampling frequency according to the frequency plan and the off chip RF/IF filters. No PLL and VCO reconfiguration is need.","PeriodicalId":446381,"journal":{"name":"2008 IEEE/ION Position, Location and Navigation Symposium","volume":"216 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE/ION Position, Location and Navigation Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PLANS.2008.4569990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A reconfigurable and simultaneous dual band Galileo/GPS front-end receiver has been realized on 0.13-mum RFCMOS technology. The front-end uses only one fixed frequency PLL and VCO on a superheterodyne architecture to down-convert two RF (radio frequency) signals into two IF (intermediate frequency) signals in the range of 50 MHz to 150 Mhz. L1 and E1 signals are directly converted on one channel with one mixing stage. L2, E6, E5, E5a, E5b signals are down-converted with a double stage (two mixers) conversion. The two IF down-converted channels are filtered and then undersampled by two on chip ADC (analog to digital converter). The satellite channels can be selected and reconfigured only by changing the ADC sampling frequency according to the frequency plan and the off chip RF/IF filters. No PLL and VCO reconfiguration is need.